View AD9901KP-REEL_818063.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES Phase and Frequency Detection ECL/TTL/CMOS Compatible Linear Transfer Function No "Dead Zone" MIL-STD-883 Compliant Versions Available APPLICATIONS Low Phase Noise Reference Loops Fast-Tuning "Agile" IF Loops Secure "Hopping" Communications Coherent Radar Transmitter/Receiver Chains
Ultrahigh Speed Phase/Frequency Discriminator AD9901
PHASE-LOCKED LOOP
REFERENCE INPUT LOWPASS FILTER VCO OSCILLATOR OUTPUT
AD9901
1/N OPTIONAL 1/N PRESCALER TYPICAL OF DIGITAL PLLs
GENERAL DESCRIPTION
The AD9901 is a digital phase/frequency discriminator capable of directly comparing phase/frequency inputs up to 200 MHz. Processing in a high speed trench-oxide isolated process, combined with an innovative design, gives the AD9901 a linear detection range, free of indeterminate phase detection zones common to other digital designs. With a single +5 V supply, the AD9901 can be configured to operate with TTL or CMOS logic levels; it can also operate with ECL inputs when operated with a -5.2 V supply. The open-collector outputs allow the output swing to be matched to post-filtering input requirements. A simple current setting resistor controls the output stage current range, permitting a reduction in power when operated at lower frequencies.
A major feature of the AD9901 is its ability to compare phase/frequency inputs at standard IF frequencies without prescalers. Excessive phase uncertainty which is common with standard PLL configurations is also eliminated. The AD9901 provides the locking speed of traditional phase/frequency discriminators, with the phase stability of analog mixers. The AD9901 is available as a commercial temperature range device, 0C to +70C, and as a military temperature device, -55C to +125C. The commercial versions are packaged in a 14-lead ceramic DIP and a 20-lead PLCC. The AD9901 Phase/Frequency Discriminator is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9901/883B data sheet for specifications.
FUNCTIONAL BLOCK DIAGRAM
D REFERENCE INPUT FLIP-FLOP REFERENCE INPUT
Q
D
Q
Q REFERENCE FREQUENCY DISCRIMINATOR FLIP-FLOP Q R
OUTPUT OUTPUT
D
Q
XOR S Q OSCILLATOR FREQUENCY DISCRIMINATOR FLIP-FLOP Q
OSCILLATOR INPUT FLIP-FLOP OSCILLATOR INPUT Q
D
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9901-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
Positive Supply Voltage (+VS for TTL Operation) . . . . . +7 V Negative Supply Voltage (-VS for ECL Operation) . . . . . -7 V Input Voltage Range (TTL Operation) . . . . . . . 0 V to +5.5 V Differential Input Voltage (ECL Operation) . . . . . . . . . . 4.0 V ISET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range AD9901KQ/KP . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature2 Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150C Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300C
ELECTRICAL CHARACTERISTICS (
VS = +5.0 V [for TTL] or -5.2 V [for ECL], unless otherwise noted)
Commercial Temperature 0 C to +70 C AD9901KQ/KP
Temp INPUT CHARACTERISTICS TTL Input Logic "1" Voltage TTL Input Logic "0" Voltage TTL Input Logic "1" Current3 TTL Input Logic "0" Current3 ECL Differential Switching Voltage ECL Input Current OUTPUT CHARACTERISTICS Peak-to-Peak Output Voltage Swing4 TTL Output Compliance Range ECL Output Compliance Range IOUT Range Internal Reference Voltage AC CHARACTERISTICS Linear Phase Detection Range4 40 kHz 30 MHz 70 MHz Functionality @ 70 MHz POWER SUPPLY CHARACTERISTICS TTL Supply Current (+5.0 V)5, 6 ECL Supply Current (-5.2 V)5, 6 Nominal Power Dissipation Full Full Full Full Full Full Full Full Full Full Full
Test Level VI VI VI VI VI VI VI V V V VI
Min 2.0
Typ
Max
Units V V mA mA mV A V V V mA V
0.8 0.6 1.6 300 20 1.6 1.8 3-7 2 0.9-11 0.47 2.0
0.42
0.52
+25C +25C +25C +25C +25C Full +25C Full +25C
V V V I I I I I V
360 320 270 Pass/Fail 43.5 43.5 42.5 42.5 218 54.0 54.0 52.5 52.5
Degrees Degrees Degrees
mA mA mA mA mW
NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Maximum junction temperature should not exceed +175 C for ceramic packages, +150C for plastic packages. Junction temperature can be calculated by: tJ = PD ( JA) +tA = PD (JC) +tC where: PD = power dissipation JA = thermal impedance from junction to air (C/W) JC = thermal impedance from junction to case ( C/W) tA = ambient temperature (C) tC = case temperature (C) typical thermal impedances: AD9901 Ceramic DIP = JA = 74C/W; JC = 21C/W AD9901 LCC = JA = 80C/W; JC = 19C/W AD9901 PLCC = JA = 88.2C/W; JC = 45.2C/W 3 VL = +0.4 V; VH = +2.4 V. 4 RSET = 47.5 ; R L = 182 . 5 lncludes load current of 10 mA (load resistors = 182 ). 6 Supply should remain stable within 5% for normal operation. Specifications subject to change without notice.
-2-
REV. B
AD9901
INPUT/OUTPUT EQUIVALENT CIRCUITS
(Based on DIP Pinouts)
TTL MODE = +VS (+5.0V) ECL MODE = GROUND +5.0V
VCO/REF, INPUT 5/12
VCO/REF, INPUT
4/13
VCO/REF, INPUT
3/14
0.47V REFERENCE -5.2V
RSET
TTL MODE = GROUND ECL MODE = VS (-5.2V)
TTL Input
ECL Input
Output
AD9901 BURN-IN CIRCUIT
(Based on DIP ECL Pinouts)
DIE LAYOUT AND MECHANICAL INFORMATION
REFERENCE IN (-VS) GND (REFERENCE IN) +VS (GND) OUTPUT RSET
DA3
VMID 1k 180 50
-VS (-5.2V) 0.01 F
GND (REFERENCE IN)
GND (-VS)
GND (-VS) VS (-VS) GND (VCO IN) +VS (GND)
GND (VCO IN)
VCO IN (-VS)
OUTPUT
AD9901
REG
DA2
1k VMID
180
ECL HIGH DA2 ECL LOW ECL HIGH DA3 ECL LOW
ALL RESISTORS 5% ALL CAPACITORS 20% ALL SUPPLY VOLTAGES VMID = -1.3V 5%
5%
STATIC: DA2 = ECL HIGH; DA3 = ECL LOW DYNAMIC: ECL HIGH
Die Dimensions . . . . . . . . . . . . . . . . . 63 x 118 x 16 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil Aluminum; Ultrasonic Bonding
ORDERING GUIDE
Model
AD9901KQ AD9901KP AD9901TQ/883 1 AD9901TE/8831
Temperature Ranges
0C to +70C 0C to +70C -55C to +125C -55C to +125C
Package Descriptions
14-Lead Cerdip 20-Lead Plastic Leaded Chip Carrier 14-Lead Cerdip 20-Terminal Ceramic Leadless Chip Carrier
Package Options
Q-14 P-20A Q-14 E-20A
NOTE 1 For specifications, refer to Analog Devices Military Products Databook.
REV. B
-3-
AD9901
TTL/CMOS MODE FUNCTIONAL PIN DESCRIPTIONS ECL MODE FUNCTIONAL PIN DESCRIPTIONS
GROUND
Ground connections for AD9901. Connect all grounds together and to low impedance ground plane as close to the device as possible. Positive supply connection; nominally +5.0 V for TTL operation. Connect to +VS (+5 V) for TTL operation. TTL compatible input; normally connected to the VCO output signal. VCO INPUT and REFERENCE INPUT are equivalent to one another. The noninverted output. In TTL/CMOS mode, the output swing is approximately +3.2 V to +5 V. External RSET connection. The current through the RSET resistor is equal to the maximum full-scale output current. RSET should be connected to ground through an external resistor in TTL mode. ISET = 0.47 V/RSET = ILOAD (max). The inverted output. In TTL/CMOS mode, the output swing is approximately +3.2 V to +5 V. TTL compatible input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent.
-VS BIAS VCO INPUT
Negative supply connection, nominally -5.2 V for ECL operation. Connect to -5.2 V for ECL operation. Inverted side of ECL compatible differential input, normally connected to the VCO output signal. Noninverted side of ECL-compatible differential input, normally connected to the VCO output signal. The noninverted output. In ECL mode, the output swing is approximately 0 V to -1.8 V. Ground connections for AD9901. Connect all grounds together and to low-impedance ground plane as close to the device as possible. External RSET connection. The current through the RSET resistor is equal to the maximum full-scale output current. RSET should be connected to -VS through an external resistor in ECL mode. ISET = 0.47 V/RSET = ILOAD (max). The inverted output. In ECL mode, the output swing is approximately 0 V to -1.8 V. Noninverted side of ECL-compatible differential input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent to one another. Inverted side of ECL-compatible differential input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent.
-VS REFERENCE REFERENCE INPUT -VS INPUT R2 OUTPUT R1 RSET
+VS BIAS VCO INPUT
VCO INPUT
OUTPUT GROUND
OUTPUT
RSET
RSET
OUTPUT
OUTPUT REFERENCE INPUT
REFERENCE INPUT
REFERENCE INPUT
+VS R2 REFERENCE OUTPUT +VS OUTPUT R1 RSET
AD9901
AD9901
REG
REG
BIAS +VS
VCO INPUT
OUTPUT R3 +VS
+VS
BIAS -VS
VCO VCO -VS OUTPUT INPUT INPUT R3
Figure 1. TTL Mode (Based on DIP Pinouts)
Figure 2. ECL Mode (Based on DIP Pinouts)
-4-
REV. B
AD9901
EXPLANATION OF TEST LEVELS
Test Level I - 100% production tested. II - 100% production tested at +25C, and sample tested at specified temperatures. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing.
V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
PIN CONFIGURATIONS TTL DIP Pinouts
GROUND 1 BIAS 2 GROUND 3
14 13
ECL DIP Pinouts
-VS 1 BIAS 2 VCO INPUT
3 14 13
GROUND GROUND REFERENCE INPUT
REFERENCE INPUT REFERENCE INPUT -VS GROUND
AD9901
12
AD9901
12 11
GROUND 4 TOP VIEW 11 +VS (Not to Scale) 10 VCO INPUT 5 OUTPUT OUTPUT 6 +VS 7
9 8
VCO INPUT 4
TOP VIEW (Not to Scale) 10 -VS 5 OUTPUT
9 8
RSET GROUND
OUTPUT 6 GROUND 7
RSET -VS
ECL LCC Pinouts
REFERENCE INPUT REFERENCE INPUT
TTL LCC Pinouts
GROUND GROUND GROUND
BIAS
NC
BIAS
3
-VS
2
3
2
1
20 19
NC
1
20 19
GROUND 4 NC 5 GROUND 6 NC 7 VCO INPUT 8 NC = NO CONNECT
9 10 11 12 13
18
REFERENCE INPUT NC +VS NC OUTPUT VCO INPUT 4 NC 5 VCO INPUT 6 NC 7 -VS 8
18
AD9901
TOP VIEW (Not to Scale)
17 16 15 14
-VS NC GROUND NC OUTPUT
AD9901
TOP VIEW (Not to Scale)
17 16 15 14
NC
GROUND
OUTPUT
+VS
RSET
NC = NO CONNECT
9
10 11 12 13
OUTPUT
GROUND
NC NC
1
-VS REFERENCE INPUT
20
TTL PLCC Pinouts
GROUND GROUND GROUND
ECL PLCC Pinouts
REFERENCE INPUT
19 18 17
BIAS
3
2
NC
1
20
19
BIAS
GROUND 4 GROUND 5 VCO INPUT 6 OUTPUT 7 NC 8 NC = NO CONNECT
9 10 11
PIN 1 IDENTIFIER
18 17
REFERENCE INPUT NC +VS NC OUTPUT VCO INPUT 4 VCO INPUT 5 -VS 6 OUTPUT 7 NC 8 NC = NO CONNECT
3
AD9901
TOP VIEW (Not to Scale)
16 15 14
-VS
2
PIN 1 IDENTIFIER
RSET
-VS NC GROUND NC OUTPUT
AD9901
TOP VIEW (Not to Scale)
16 15 14
12
13
NC
GROUND
+VS
NC
RSET
9
10
11
12
13
NC
GROUND
NC
-VS
REV. B
-5-
RSET
AD9901
THEORY OF OPERATION
A phase detector is one of three basic components of a phaselocked loop (PLL); the other two are a filter and a tunable oscillator. A basic PLL control system is shown in Figure 3.
REFERENCE INPUT LOWPASS FILTER VCO OSCILLATOR OUTPUT
REFERENCE INPUT OSCILLATOR INPUT REFERENCE FLIP-FLOP OUTPUT OSCILLATOR FLIP-FLOP OUTPUT XORGATE OUTPUT
DC MEAN VALUE
AD9901
1/N OPTIONAL 1/N PRESCALER TYPICAL OF DIGITAL PLLs
Figure 6. Timing Waveforms (OUT Lags IN)
Figure 3. Phase-Locked Loop Control System
The function of the phase detector is to generate an error signal that is used to retune the oscillator frequency whenever its output deviates from a reference input signal. The two most common methods of implementing phase detectors are (1) an analog mixer and (2) a family of sequential logic circuits known as digital phase detectors. The AD9901 is a digital phase detector. As illustrated in the block diagram of the unit, straightforward sequential logic design is used. The main components include four "D" flip-flops, an exclusive-OR gate (XOR) and some combinational output logic. The circuit operates in two distinct modes: as a linear phase detector and as a frequency discriminator. When the reference and oscillator are very close in frequency, only the phase detection circuit is active. If the two inputs are substantially different in frequency, the frequency discrimination circuit overrides the phase detector portion to drive the oscillator frequency toward the reference frequency and put it within range of the phase detector. Input signals to the AD9901 are pulse trains, and its output duty cycle is proportional to the phase difference of the oscillator and reference inputs. Figures 4, 5 and 6 illustrate, respectively, the input/output relationships at lock; with the
REFERENCE INPUT OSCILLATOR INPUT REFERENCE FLIP-FLOP OUTPUT OSCILLATOR FLIP-FLOP OUTPUT XORGATE OUTPUT
oscillator leading the reference frequency; and with the oscillator lagging. This output pulse train is low-pass filtered to extract the dc mean value [K (I - O)] where K is a proportionality constant (phase gain). At or near lock (Figures 4, 5 and 6), only the two input flipflops and the exclusive-OR gate (the phase detection circuit) are active. The input flip-flops divide both the reference and oscillator frequencies by a factor of two. This insures that inputs to the exclusive-OR are square waves, regardless of the input duty cycles of the frequencies being compared. This division-by-two also moves the nonlinear detection range to the ends of the range rather than near lock, which is the case with conventional digital phase detectors. Figure 7 illustrates the constant gain near lock.
2 FO = 70MHz OUTPUT VOLTAGE SWING
FO = 200MHz
FO = 50MHz
1
TYPICAL PHASE DETECTOR GAIN IS 0.2865V/RAD VOUT = 1.8V
0 -2
- PHASE DIFFERENCE AT INPUTS
0
Figure 7. Phase Gain Plot
DC MEAN VALUE
Figure 4. AD9901 Timing Waveforms at "Lock"
REFERENCE INPUT OSCILLATOR INPUT REFERENCE FLIP-FLOP OUTPUT OSCILLATOR FLIP-FLOP OUTPUT XORGATE OUTPUT
When the two square waves are combined by the XOR, the output has a 50% duty cycle if the reference and oscillator inputs are exactly 180 out of phase; under these conditions, the AD9901 is operating in a locked mode. Any shift in the phase relationship between these input signals causes a change in the output duty cycle. Near lock, the frequency discriminator flipflops provide constant HIGH levels to gate the XOR output to the final output. The duty cycle of the AD9901 is a direct measure of the phase difference between the two input signals when the unit is near lock. The transfer function can be stated as [K(I - O](V/RAD), where K is the allowable output voltage range of the AD9901 divided by 2 .
DC MEAN VALUE
Figure 5. Timing Waveforms ( OUT Leads IN)
For a typical output swing of 1.8 V, the transfer function can be stated as (1.8 V/2 = 0.285 V/RAD). Figure 7 shows the relationship of the dc mean value of the AD9901 output as a function of the phase difference of the two inputs. -6- REV. B
AD9901
500mV
100 90 100 90
500mV
100 90
500mV
10 0%
10 0%
10 0%
200ns
200ns
5ns
Figure 8. AD9901 Output Waveform (FO << FI )
Figure 9. AD9901 Output Waveform (FO >> FI )
165 155 145
VCO FREQUENCY - MHz
Figure 10. AD9901 Output Waveform (FO = FI = 50 MHz)
It is important to note that the slope of the transfer function is constant near its midpoint. Many digital phase comparators have an area near the lock point where their gain goes to zero, resulting in a "dead zone." This causes increased phase noise (jitter) at the lock point. The AD9901 avoids this dead zone by shifting it to the endpoints of the transfer curve, as indicated in Figure 7. The increased gain at either end increases the effective error signal to pull the oscillator back into the linear region. This does not affect phase noise, which is far more dependent upon lock region characteristics. It should be noted, however, that as frequency increases, the linear range is decreased. At the ends of the detection range, the reference and oscillator inputs approach phase alignment. At this point, slew rate limiting in the detector effectively increases phase gain. This decreases the linear detection by nominally 3.6 ns. Therefore, the typical detection range can be found by calculating [(1/F - 3.6 ns)/(1/F)] x 360. As an example, at 200 MHz the linear phase detection range is 50. Away from lock, the AD9901 becomes a frequency discriminator. Any time either the reference or oscillator input occurs twice before the other, the Frequency High or Frequency Low flip-flop is clocked to logic LOW. This overrides the XOR output and holds the output at the appropriate level to pull the oscillator toward the reference frequency. Once the frequencies are within the linear range, the phase detector circuit takes over again. Combining the frequency discriminator with the phase detector eliminates locking to a harmonic of the reference. Figure 8 shows the effect of the "Frequency Low" flip-flop when the oscillator frequency is much lower than the reference input. The narrow pulses, which result from cycles when two positive reference-input transitions occur before a positive VCO edge, increase the dc mean value. Figure 9 illustrates the inverse effect when the "Frequency High" flip-flop reacts to a much higher VCO frequency. Figure 10 shows the output waveform at lock for 50 MHz operation. This output results when the phase difference between reference and oscillator is approximately - Rad.
AD9901 APPLICATIONS
135 125 115 105 95 85 75 65 -1 0 1 2 3 4 5 VARACTORS TUNING VOLTAGE - Volts 6
Figure 11. VCO Frequency vs. Voltage
Next, the range of frequencies over which the VCO is to operate is examined to assure that it lies on a linear portion of the transfer curve. In this case, frequencies from 100 MHz to 120 MHz result from tuning voltages of approximately +1.5 V to +2.5 V. Because the nominal output swing of the AD9901 is 0 V to -1.8 V, an inverting amplifier with a gain of 2 follows the loop filter. As shown in the illustration, a simple passive RC low-pass filter made up of two resistors and a tantalum capacitor eliminates the need for an expensive high speed op amp active-filter design. In this passive-filter second-order-loop system, where n = 2, the damping factor is equal to: = 0.5 [KOK d /n(1 + 2)]1/2 [2 + (n/KO Kd)] and the values for 1 and 2 are the low-pass filter's time constants R1C and R2C. The gain of 2 of the inverting stage, when combined with the phase detector's gain, gives: Kd = 0.572 V/RAD With KO = 115.2 MRAD/s/V, 1 equals 1.715s, and 2 equals 3.11 x 10-4s for the required damping factor of 0.7. The illustrated values of 30 (R1), 160 (R2), and 10 F (C) in the diagram approximate these time constants. The gain of the RC filter is: VO/VI = (1 + sR2C)/[1 + s(R1 + R2)C]. Where KOKd >> n, the system's natural frequency: n = [KOK d /n(1 + 2)]1/2 = 4.5 kHz. For general information about phase-locked loop design, the user is advised to consult the following references: Gardner, Phase-Lock Techniques (Wiley); or Best, Phase Locked Loops (McGraw-Hill).
The figure below illustrates a phase-locked loop (PLL) system utilizing the AD9901. The first step in designing this type of circuit is to characterize the VCO's output frequency as a function of tuning voltage. The transfer function of the oscillator in the diagram is shown in Figure 11. REV. B
-7-
AD9901
+VS REFERENCE INPUT 55MHz +5.0V OUTPUT OUTPUT OSC AD96685 OFFSET -5.2V -5.2V REF 182 REF OUT OUT 160k 30 RSET -5.2V 10 F LOOP FILTER OSCILLATOR OUTPUT 110MHz MV1404 DIVIDEBY-TWO ALTERNATE HIGH LEVEL OUTPUT CIRCUIT ( VS TYPICALLY +15V TO +60V) 50 50 -5.2V -2V -2V 50 -5.2V OSCILLATOR MC1648 100nH 51k MV1404 AD741 390 AD741 1k 1k -5.2V 2k
AD9901
OSC 47.5
AD9901
DIP PINOUTS
Figure 12. Phased-Locked Loop Using AD9901
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip (Q-14)
0.005 (0.13) MIN
14
0.098 (2.49) MAX
8
0.310 (7.87) 0.220 (5.59)
1 7
PIN 1 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.150 (3.81) MIN 0.100 0.070 (1.78) SEATING PLANE (2.54) 0.030 (0.76) BSC
15 0
0.015 (0.38) 0.008 (0.20)
20-Terminal Ceramic Leadless Chip Carrier (E-20A)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.200 (5.08) BSC 0.100 (2.54) BSC
3 4 1
20-Lead Plastic Leaded Chip Carrier (P-20A)
0.180 (4.57) 0.165 (4.19)
19 18 20
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
0.358 (9.09) 0.358 (9.09) 0.342 (8.69) MAX SQ SQ
0.048 (1.21) 0.042 (1.07)
3 4
19 18 PIN 1 IDENTIFIER
BOTTOM VIEW
14 13 8 9
TOP VIEW
(PINS DOWN) 8 9 14 13
0.050 (1.27) BSC
0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
0.088 (2.24) 0.054 (1.37)
0.055 (1.40) 0.045 (1.14)
45 TYP 0.150 (3.81) BSC
0.020 (0.50) R
0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78)
-8-
REV. B
PRINTED IN U.S.A.
0.100 (2.54) 0.064 (1.63)
0.048 (1.21) 0.042 (1.07)
0.056 (1.42) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38)
C1272b-0-1/99
This datasheet has been download from: www..com Datasheets for electronics components.

▲Up To Search▲

Price & Availability of AD9901KP-REEL

	To Download AD9901KP-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .